Design and Implementation of Low-Power Digit-Serial Multipliers

Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel design methodology is presented which permits bit-level pipelining of the digit-serial ar-chitectures. This enables bit-level pipelining of digit-serial architectures thereby achieving sample speeds close to corresponding bit-parallel multipliers with sig-niicantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in signiicant reduction in power consumption. The results show that for transformed multipliers with smaller digit-sizes (4), the singly-redundant multi-plier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is p 2W, where W represents the word-length. The proposed digit-serial multipliers consume on an average 20% lower power than the traditional digit-serial archi-tectures for the non-pipelined case, and about 5 ? 15 times lower power for the bit-level pipelined case. Also, modiied Booth recoding is applied to transformed mul-tipliers and it is found that the recoded multipliers consume about 22% lower power than the transformed mul-tipliers without recoding.